A fabrication process for integrating polysilicon microstructures with post-processed CMOS circuits

A MEMS-first fabrication process for integrating CMOS circuits with polysilicon micromechanical structures is described in detail. The overall process uses 18 masks (22 lithography steps) to merge a p-well LOCOS CMOS process that has one metal and two polysilicon layers with a surface micromachining process that has three layers of polysilicon. The microstructures are formed within recesses on the surface of silicon wafers such that their uppermost surfaces are coplanar with the remainder of the substrate. No special planarization technique, such as chemical–mechanical polishing, is used in the work described here. Special aspects of the process include provisions to improve lithography within the recesses, to protect the microstructures during the circuit fabrication, and to implement an effective lead transfer between the microstructures and the on-chip circuitry. The process is validated using a test vehicle that includes accelerometers and gyroscopes interfaced with sensing circuits. Measured transistor parameters match those obtained in standard CMOS, with NMOS and PMOS thresholds at 0.76 V and −0.96 V, respectively.